HOW COMPUTE WORKSBy Michael Hsu

GPU package

What is a silicon interposer?

This layer provides fine electrical connections between the compute dies and memory. It helps these separate chips work together in one package.

Explore it in the 3D GPU model

What it does

This layer provides fine electrical connections between the compute dies and memory. It helps these separate chips work together in one package.

Why it sits where it does

It sits directly beneath the chips and above the package substrate. The interposer connects closely spaced chip contacts; the substrate connects the assembly toward the larger board.

How it works

Small conductive paths carry electrical signals between chips.

Limits and trade-offs

Fine connections need precise manufacturing and assembly. An interposer is one packaging approach, and different products use different layouts and materials.

In Blackwell Ultra and MI300X

NVIDIA Blackwell Ultra

A molded RDL interposer sits beneath the chips. Embedded local silicon bridges provide dense connections near adjacent die edges.

Local silicon bridges handle dense nearby links. Copper redistribution layers and vertical interconnects carry signals and power through the package.

See it in the NVIDIA Blackwell Ultra model

AMD MI300X

A passive silicon interposer sits below the active I/O dies and HBM, above the substrate.

Fine lateral wiring joins I/O dies and memory. TSVs carry connections vertically through the silicon interposer toward the substrate; lateral die-to-die paths need not traverse those TSVs.

See it in the AMD MI300X model

How it is made

  1. Form fine conductive paths on silicon, with vertical connections where the design needs them.
  2. Align and connect the compute and memory chips to that layer.
  3. Integrate the assembly with the substrate and test its connections.

How it developed

  1. Early 2010s

    Connecting separate chips in one package

    TSMC announced a CoWoS test vehicle combining a processor and memory on one interposer.

    TSMC · CoWoS test vehicle announcement ↗
  2. Recent variants

    Different ways to build the connection layer

    TSMC added two CoWoS variants. CoWoS-R uses redistribution layers; CoWoS-L adds embedded local silicon interconnects, as shown in the Blackwell schematic.

    TSMC · CoWoS packaging options and production history ↗

Where it is used

Key terms

Interposer
A connection layer placed between chips and their supporting package.

Sources

The 3D models are illustrative teaching schematics, not manufacturer CAD. Counts and layouts are simplified where the sources say so.

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