GPU package
What does a GPU package substrate do?
Bare silicon needs a way to connect to a larger system. The package substrate supports the assembly and routes connections toward the circuit board. It belongs beneath the chips because it bridges their compact assembly and the board that carries the system. The model groups several routing layers for clarity; a substrate and a fine-pitch interposer are not the same component.
Explore it in the 3D GPU modelWhat it does
The substrate supports the package and routes electrical connections toward the circuit board. It gives the smaller chips a practical connection to the larger system.
Why it sits where it does
It forms the bottom of the package, beneath the interposer. In this model, solder contacts underneath connect the package to a board.
Connections inside a multi-chip package operate at a different physical scale from the connections on the system board. Packaging bridges those scales.
How it works
Multiple layers carry connections through the package. The interposer handles fine connections near the chips; the substrate carries connections toward the board. They have different jobs.
Limits and trade-offs
The substrate must fit many connections into a small area while supporting the assembly.
More chips and connections require increasingly complex routing and reliable assembly.
In Blackwell Ultra and MI300X
NVIDIA Blackwell Ultra and AMD MI300X
The organic substrate distributes power and ground, supports the assembly and fans signals out to the board. Nearby decoupling capacitors help stabilize voltage during load changes.
How it is made
- Build an insulating base with several layers of conductive connections.
- Add the contacts needed to join it to the rest of the package and board.
- Assemble and test the finished package.
How it developed
- From chips to systems
Packaging becomes part of the architecture
Advanced packages combine logic and memory through multiple connection layers. Their arrangement affects how an entire system can be built.
SK hynix · How wafer-level packages are made ↗ - Early 2010s
A bridge from assembled chips to a package
TSMC described bonding chips to a wafer and attaching the resulting chip assembly to a substrate. This illustrates the substrate’s separate role underneath the chip assembly.
TSMC · CoWoS test vehicle announcement ↗
Where it is used
TSMC CoWoS
Packaging platform
TSMC builds CoWoS packages several times the size of one reticle, with larger versions on its roadmap.
TSMC · Logic and packaging roadmap, April 2026 ↗Substrates in CoWoS packages
Packaging example
A CoWoS package brings chips, interconnect structures, and a substrate together.
TSMC · CoWoS test vehicle announcement ↗
Key terms
- Substrate
- The supporting base that carries connections through a package.
Sources
- TSMC · CoWoS packaging options and production history ↗
- TSMC · CoWoS test vehicle announcement ↗
- SK hynix · How wafer-level packages are made ↗
- TSMC · Logic and packaging roadmap, April 2026 ↗
- NVIDIA · Inside Blackwell Ultra, August 2025 ↗
- Micron · HBM3E stack and interface ↗
- AMD · MI300 architecture and cache hierarchy ↗
- AMD · Instinct GPU specifications ↗
The 3D models are illustrative teaching schematics, not manufacturer CAD. Counts and layouts are simplified where the sources say so.